Title :
An 830mW, 586kbps 1024-bit RSA chip design
Author :
Yeh, Chingwei ; Hsu, En-Feng ; Cheng, Kai-Wen ; Wang, Jinn-Shyan ; Chang, Nai-Jen
Author_Institution :
Nat. Chung-Cheng Univ., Chia-Yi
Abstract :
This paper presents an RSA hardware design that simultaneously achieves high-performance and low-power. A bit-oriented, split modular multiplication algorithm and architecture are proposed to fully exert the radix-4 computational capability. Further, we identify the switching profile of RSA data and accordingly propose power-optimized designs for the storage elements and key computational components. The complete RSA modular exponentiation hardware has been implemented using cell-based 0.18mum CMOS technology. Post-layout simulation shows that the design delivers an average performance of 586kbps at 460MHz, 1.8Vwhile consuming only 830mW
Keywords :
CMOS digital integrated circuits; cryptography; digital arithmetic; logic design; low-power electronics; microprocessor chips; 0.18 micron; 1.8 V; 1024 bit; 460 MHz; 586 kbit/s; 830 mW; CMOS technology; RSA hardware design; modular exponentiation hardware; power-optimized designs; radix-4 computational capability; split modular multiplication algorithm; storage elements; switching profile; Application specific integrated circuits; CMOS technology; Chip scale packaging; Computational modeling; Computer architecture; Computer networks; Hardware; Interleaved codes; Kernel; Public key cryptography;
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
DOI :
10.1109/DATE.2006.244159
