Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time

Mask programmable gate arrays (MPGAs) see a growing importance because of the increase of design cost and turnaround times in ultra-deep submicron technologies which mostly impact ASICs. Several design methodologies have been proposed in recent years for converting an evaluated field-programmable gate-array (FPGA) prototype-design into an MPGA. An automatic conversion flow is essential to success. In this paper, we present a conversion flow for a look-up table-based (LUT-based) MPGA without applying re-synthesis but preserving the gate-level netlist and reusing the placement. The resulting flow has a special routing tool and buffer insertion algorithm for timing integrity. The experimental investigations use a commercial FPGA and industrial benchmarks