ASIP Architecture for Multi-Standard Wireless Terminals

Author

Iacono, D. Lo ; Zory, J. ; Messina, E. ; Piazzese, N. ; Saia, G. ; Bettinelli, A.

Volume

2

fYear

2006

fDate

6-10 March 2006

Firstpage

1

Lastpage

6

Abstract

This paper presents the block processing engine (BPE), an application specific instruction-set processor (ASIP) explicitly designed for the implementation of multi-standard wireless terminals. Thanks to a high level of parallelism and a consistent use of pipeline, the BPE architecture fully satisfies stringent real-time constraints imposed by emerging technologies. Its efficiency has been proven through the implementation, the physical synthesis for the CMOS 90nm STM technology and the FPGA prototyping on the ARM Versatile platform of a dual-standard frequency domain equalizer (FDE) supporting the 3GPP HSDPA and the IEEE 802.11a standards

Keywords

IEEE standards; application specific integrated circuits; field programmable gate arrays; integrated circuit design; logic design; microprocessor chips; mobile radio; packet radio networks; 3GPP HSDPA; 90 nm; ASIP architecture; CMOS technology; FPGA prototyping; IEEE 802.11a standards; application specific instruction-set processor; block processing engine; frequency domain equalizer; multistandard wireless terminals; Application specific processors; CMOS technology; Engines; Equalizers; Field programmable gate arrays; Frequency domain analysis; Multiaccess communication; Pipelines; Process design; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings

Conference_Location

Munich

Print_ISBN

3-9810801-1-4

Type

conf

DOI

10.1109/DATE.2006.243814

Filename

1657125