Delay minimisation in CMOS combinational arithmetic circuits for low power

Author

Dinesh, B. ; Jagadeesh, R. ; Kathirvelu, M.

Author_Institution

Dept. of ECE, KPR Inst. of Eng. & Technol., Coimbatore, India

fYear

2014

fDate

13-14 Feb. 2014

Firstpage

1

Lastpage

7

Abstract

Power consumption in digital systems has become a major trade-off in portable battery based digital systems. Traditionally CMOS logic circuits are used to manufacture digital systems and the power delay product gives the average power consumed per unit switching activity in a CMOS logic. A power and delay reduction methodology based on DEMORGAN´S Laws is proposed and the proposed logical block is implemented on a 4×4 array multiplier using 45nm technology. The proposed logic based multiplier shows 20% reduction in power, 50% reduction in delay and 50% reduction in PDP compared to a standard 4×4 array multiplier.

Keywords

CMOS logic circuits; combinational circuits; combinational switching; digital arithmetic; low-power electronics; minimisation; multiplying circuits; CMOS combinational arithmetic circuit; CMOS logic circuit; DEMORGAN´s law; PDP; delay minimisation; delay reduction methodology; digital system; logic based multiplier; low power electronics; portable battery; power consumption; power delay product; power reduction methodology; size 45 nm; Adders; Arrays; CMOS integrated circuits; Delays; Logic gates; Power demand; Transistors; DEMORGAN´S laws; Low power; Reduced PDP; Reduced delay;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics and Communication Systems (ICECS), 2014 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-2321-2

Type

conf

DOI

10.1109/ECS.2014.6892811

Filename

6892811