Title :
Design and evaluation of virtual channel router for mesh-of-grid based NoC
Author :
Anjali, N.V. ; Somasundaram, K.
Author_Institution :
Dept. of ECE, Amrita Sch. of Eng., Coimbatore, India
Abstract :
Network on Chips (NoCs) has now replaced the bus based architectures for communication between different cores in a multiprocessor System on Chip (SoC). NoC integrates SoCs in a better manner. It has the advantage of good scalability and high bandwidth. The communication on NoC is carried out by means of routers. Routers are the back bone of NoC. The design of routers is different for different topologies. In this paper, a Mesh-of-Grid topology is considered. A virtual channel router for mesh of grid topology of NoC is presented here. Area and Power is synthesized for the virtual channel router using Synopsys Design Vision. The experimental results show that the area and power will increase if the bit size of flit is increased.
Keywords :
CMOS integrated circuits; hardware description languages; integrated circuit design; integrated circuit interconnections; network routing; network-on-chip; CMOS technology; Synopsys Design Vision; Verilog HDL; mesh-of-grid topology; network on chips; virtual channel router; Network topology; Ports (Computers); Routing; Routing protocols; Switches; System-on-chip; Topology; Network on Chip; mesh of grid; router; virtual channel router;
Conference_Titel :
Electronics and Communication Systems (ICECS), 2014 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-2321-2
DOI :
10.1109/ECS.2014.6892817
