Area efficient high and low pass filter design for DWT applications

In this paper the Field Programmable Gate Array (FPGA) is discussed with the implementation of high and low pass filters using their application in discrete wavelet transform (DWT) for biomedical applications. The implementation is based on bit serial approach (BS) which substitute multiply and accumulate operations with a series of lookup- table (LUT) accesses. BS provides a multiplication-free method for calculating inner products of fixed-point data, based on table lookups of pre-calculated partial products. But increase in filter order leads complexity. Here the implementation results of a high-speed and low power architecture is proposed. The proposed MUX based LUT less filter is implemented in hardware description language and verified via simulation. The proposed architecture scheme yields significantly reduced complexity, less area and high speed features.