A Novel FPGA-based Implementation of Time Adaptive Clustering for Logical Story Unit Segmentation

Author

Arifin, Sutjipto ; Cheung, Peter Y K

Author_Institution

Dept. of EEE, Imperial Coll. London

Volume

2

fYear

2006

fDate

6-10 March 2006

Firstpage

1

Lastpage

6

Abstract

Time adaptive clustering (TAC) is a cognitive logical story unit (LSU) segmentation algorithm that is found to show good and consistent results. This paper presents an efficient hardware implementation for approximating the TAC algorithm. The design consists of three main blocks. The first block generates similarity values needed in the clustering process. To take full advantage of the parallelism of field programmable gate arrays (FPGA) devices, a video shot sequence is divided into subsets and processed in parallel by the second block. The third block combines all the output results of each subset. The design is implemented on a Xilinx Virtex-II xc2v3000 on board a RC203E board and it runs 27 times faster than a Pentium 4-based PC at 3.4 Ghz

Keywords

coprocessors; field programmable gate arrays; image segmentation; integrated logic circuits; pattern clustering; FPGA; RC203E board; TAC algorithm; Virtex-II xc2v3000; Xilinx; field programmable gate arrays device; logical story unit segmentation; similarity value generation; time adaptive clustering; Broadband communication; Circuits and systems; Clustering algorithms; Educational institutions; Field programmable gate arrays; Hardware; Motion pictures; Time factors; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 2006. DATE '06. Proceedings

Conference_Location

Munich

Print_ISBN

3-9810801-1-4

Type

conf

DOI

10.1109/DATE.2006.243907

Filename

1657145