Title :
A localized self-resetting gate design methodology for low power
Author :
Kim, Woo Jin ; Kim, Yong-Bin
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
In this paper, a modification of the traditional dynamic self-reset circuitry is introduced for low power SRAM circuit design. The reset circuitry is localized, and the negative (trailing) trigger edge of the data is used to generate the self-reset signal to avoid the problem of crowbar current from VDD to VSS. It is demonstrated that fanouts of 6<Finter<10, and 4<F out<7 give the best delay-product values for a 0.5 um CMOS process
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit design; logic design; logic gates; low-power electronics; 0.5 micron; CMOS process; crowbar current; delay-product value; dynamic circuit; fanout; localized self-resetting logic gate design; low power SRAM; CMOS logic circuits; Delay; Design methodology; Driver circuits; Logic arrays; Logic circuits; Pulse circuits; Pulse generation; Signal generators; Variable structure systems;
Conference_Titel :
Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on
Conference_Location :
Dayton, OH
Print_ISBN :
0-7803-7150-X
DOI :
10.1109/MWSCAS.2001.986174
