A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture

This paper presents a new digital background calibration algorithm for 2.5bits/stage pipelined analog-to-digital converters (ADCs) with opamp sharing architecture. Background calibration can extract calibration data without interrupting ADCs normal conversion operation. Digital calibration can relax the design difficulty of analog circuits of ADCs, and gains the improvement of technology scaled down. This algorithm provides a method to effectively estimate the nonlinearity of opamp, and calibrates it in digital domain. For a 10bit 2.5bit/stage pipelined ADCs with opamp sharing architecture, only one opamp need to be calibrated to achieve 10bit resolution. Simulation results show that the ENOB can be improved from 5.54b to 8.80b by the proposed algorithm.