A low latency high throughput router for On-Chip interconnect networks

A low latency high throughput Dynamic Virtual Output Queues Router for On-Chip interconnect networks is proposed in this paper, which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output queues scheme. Compared to wormhole router and virtual channel router, Simulation results show that network throughput on a 4×4 mesh increases by up to 46.□2 and 81.62 respectively, and outperforms doubled buffer virtual channel by N□2 under same input speedup, z etwork 5ero-load-latency also decreases by 8T.62 and 4N2 respectively under random traffic. Synthesis results in MS0 C 6Tnm technology indicate the frequency of router with G4G4mm⁸ area can reach 8.THF 5.