Low-power digital filter implementations using ternary coefficients

We propose an efficient design procedure for digital FIR filters whose coefficients are restricted to the ternary set (-1, 0, +1), cascaded by a multiplication-free architecture. A dynamic programming algorithm, minimizing the instantaneous error, is also proposed to assist in the search for the optimal ternary filter coefficient set. Power reductions in a VLSI implementation appear feasible, when compared to other published approaches