Reconfigurable adders for Binary/BCD addition/subtraction

In this paper a new reconfigurable architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented. The architecture is mainly designed keeping in mind the signed magnitude format. The proposed architecture avoids the usage of additional 2´s complement and 10´s complement circuitry, for correcting the results to sign magnitude format. The architecture is run-time reconfigurable to facilitate both BCD and Binary operations. Simulation results show that the proposed architecture is 13.6% better in terms of delay than the existing designs.