RISC system design in an FPGA

Author

Luker, Jarrod D. ; Prasad, Vinod B.

Volume

2

fYear

2001

fDate

2001

Firstpage

532

Abstract

Known for their flexibility, Field Programmable Gate Arrays (FPGA) are widely used for ASIC emulation, glue-logic consolidation, or as a solution for applications with high volatility. FPGAs facilitate quick time to market, and their incredible power of re-programmability often makes them the heart of a system. This paper presents the design of a Reduced Instruction Set Computer (RISC) system described using VHDL and the results of researching the implementation of this system in an FPGA. This RISC is a 16-bit processor with high general-purpose register (GPR) orthogonality and communicates to peripheral devices via a serial bus

Keywords

field programmable gate arrays; integrated circuit design; microprocessor chips; reduced instruction set computing; 16 bit; FPGA; RISC architecture; RISC processor; RISC system design; VHDL; field programmable gate arrays; high general-purpose register orthogonality; reduced instruction set computing; serial bus; Application software; Application specific integrated circuits; Computer aided instruction; Emulation; Field programmable gate arrays; Ground penetrating radar; Heart; Reduced instruction set computing; Registers; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986247

Filename

986247