A mixed mode neuro-VLSI chip for high speed applications

Author

Waheed, Khurram ; Salam, Fathi M.

Author_Institution

Dept. of Electr. & Comput. Eng., Michigan State Univ., East Lansing, MI, USA

Volume

2

fYear

2001

fDate

2001

Firstpage

580

Abstract

This paper presents selected design and operation details of a custom integrated neural chip. This neural processing chip is designed in the recent 0.18 μm, single poly, six-layer Cu interconnect technology. The chip realizes an architecture that achieves the task of autonomous-learning execution times in micro to milli seconds. The core consists of basic building blocks of 4-quadrant multipliers, transconductance amplifiers, and active load resistances, for analog (forward) network processing and learning modules. Super-imposed on the processing network are digital memory and control modules composed of D-Flipflops, ADC, Multiplying D/A Converter (MDAC), decoders, multiplexers and comparators for parameter (weight) storage, logical control and analog/digital conversions

Keywords

CMOS integrated circuits; VLSI; copper; high-speed integrated circuits; mixed analogue-digital integrated circuits; neural chips; 0.18 micron; 4-quadrant multipliers; ASIC; Cu; active load resistances; analog network processing; autonomous-learning; comparators; custom integrated neural chip; decoders; digital memory; high speed applications; mixed mode neuro-VLSI chip; multiplexers; multiplying DAC; single poly six-layer Cu interconnect technology; transconductance amplifiers; Application software; Communication system control; Copper; Integrated circuit interconnections; LAN interconnection; Laboratories; Neural networks; Process design; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on

Conference_Location

Dayton, OH

Print_ISBN

0-7803-7150-X

Type

conf

DOI

10.1109/MWSCAS.2001.986258

Filename

986258