C-NNAP: a dedicated platform for binary neural networks

This paper describes techniques for the hardware implementation of a Correlation Matrix Memory (CMM), which is a fundamental element of a binary neural network. For large scale problems the CMM algorithm requires dedicated accelerating hardware to maintain the processing rates required. This paper describes the C-NNAP architecture, which provides processing rates nearly eight times faster than a modern 64-bit workstation. The C-NNAP architecture hosts a dedicated FPGA processor to perform the bit summing operation. The system is modular so that multiple boards can provide a more powerful platform