An FPGA implementation of real-time QRS detection

This paper illustrates a simple algorithm for real time QRS detection from ECG data. The algorithm is implemented on Xilinx field programmable gate array using very small number of memory cells. Single lead Synthetic ECG using ptb-db database (from Physionet) is generated from a personal computer using the parallel port (LPT1) at 1 ms sampling interval and delivered to the FPGA (Field Programmable Gate Array) board. At first, from the first 1500 samples, the QRS detection algorithm calculates some characteristic amplitude and slope based signatures which are used to form a rule base. These rules are used for detecting the next incoming QRS regions accurately. The index points of R-peaks are determined and shown in the LEDs using switch-based commands.