DocumentCode :
2290571
Title :
Range Pre-filter Realization of Ground Real-time Imaging processor for Spaceborne SAR
Author :
Ma, Xiao-Bing ; Xia, Yu-Li ; Zhang, Ping
Author_Institution :
Inst. of Electron., Chinese Acad. of Sci., Beijing
fYear :
2006
fDate :
16-19 Oct. 2006
Firstpage :
1
Lastpage :
4
Abstract :
Under the condition of meeting resolution, the SAR real-time imaging processor can satisfy the demands of the processing band through pre-filter and down-sample. Because of the special position in the signal processor, ranger pre-filter needs very high operation speed and better response performance. The principles of pre-filter and the methods to achieve the pre-filter are introduced in this paper. The study, focusing on the difference between ADSP-TS101S and XC4VSX35. FPGA in implementing the high performance filter, results that FPGA has the advantage over DSP. In conclusion, the results of the practical experiments are given to illuminate the rationality of the design
Keywords :
field programmable gate arrays; filtering theory; radar imaging; spaceborne radar; synthetic aperture radar; ADSP-TS101S; FPGA; XC4VSX35; field programmable gate array; ground real-time imaging processor; range prefilter realization; spaceborne SAR; synthetic aperture radar; Algorithm design and analysis; Azimuth; Bandwidth; Digital signal processing; Displays; Field programmable gate arrays; Finite impulse response filter; Frequency estimation; Signal resolution; Signal sampling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radar, 2006. CIE '06. International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9582-4
Electronic_ISBN :
0-7803-9583-2
Type :
conf
DOI :
10.1109/ICR.2006.343163
Filename :
4148269
Link To Document :
بازگشت