Title :
Low power parallel multipliers
Author :
De Angel, Edwin ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fDate :
30 Oct-1 Nov 1996
Abstract :
This paper presents and compares sign extension techniques used to decrease the switching activity and improve the performance of parallel multipliers. A detailed review of different sign extension schemes is presented and an improved scheme for reducing the power dissipation is proposed. Four parallel CMOS multipliers designed in 0.6 μm technology are used to implement and compare the sign extension schemes
Keywords :
CMOS logic circuits; carry logic; digital arithmetic; multiplying circuits; parallel processing; thermal analysis; 0.6 micron; low power parallel multipliers; modified Booth algorithm; parallel CMOS multipliers; performance; power dissipation reduction; sign extension techniques; switching activity; Algorithm design and analysis; CMOS process; CMOS technology; Delay lines; Digital signal processors; Logic arrays; Power dissipation; Signal design; Signal processing algorithms; Very large scale integration;
Conference_Titel :
VLSI Signal Processing, IX, 1996., [Workshop on]
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-3134-6
DOI :
10.1109/VLSISP.1996.558332
