DocumentCode
2291083
Title
Optimal design and performance assessment of extremely-scaled si nanowire FET on insulator
Author
Chen, Chun-Yu ; Liao, Yi-Bo ; Chiang, Meng-Hsueh ; Keunwoo Kim ; Hsu, Wei-Chou ; Cheng, Shiou-Ying
Author_Institution
Dept. of Electron. Eng., Nat. Ilan Univ., I-Lan, Taiwan
fYear
2009
fDate
5-8 Oct. 2009
Firstpage
1
Lastpage
2
Abstract
Optimal design for nanowire FETs beyond 22 nm technology node is presented using numerical 3D simulation and physical analysis. Our results suggest that design optimization associated with the wire diameter could achieve performance benefits in the nanowire FET technologies. Small wire diameter is not necessary for performance, though it favors device scaling.
Keywords
MOSFET; nanoelectronics; nanowires; device scaling; extremely-scaled nanowire FET; numerical 3D simulation; wire diameter; Analytical models; Design optimization; Electrons; FETs; Insulation; MOSFETs; Nanoscale devices; Nanostructures; Performance analysis; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2009 IEEE International
Conference_Location
Foster City, CA
ISSN
1078-621X
Print_ISBN
978-1-4244-4256-0
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2009.5318741
Filename
5318741
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