Implementation Issues of Turbo Synchronization with Duo-Binary Turbo Decoding

The transmission over a wireless channel results in timing, frequency and phase offsets. To circumvent the severe losses of communications performance caused by these offsets a sophisticated synchronization is mandatory. Synchronization is typically performed only once prior to the channel decoding. In this paper the authors present an FPGA implementation of a joint iterative decoder and synchronizer, which is also referred to as turbo synchronizer. We investigate the additional costs of turbo synchronization in terms of implementation complexity with a 16-state duo-binary turbo decoder. Furthermore we present the communications performance of the turbo synchronizer taking the implementation losses into account.