Author :
Yang, N. ; Bulsara, M.T. ; Fitzgerald, E.A. ; Liu, W.K. ; Lubyshev, D. ; Fastenau, J.M. ; Wu, Y. ; Urteaga, M. ; Ha, W. ; Bergman, J. ; Brar, B. ; Drazek, C. ; Daval, N. ; Benaissa, L. ; Augendre, E. ; Hoke, W.E. ; Laroche, J.R. ; Herrick, K.J. ; Kazior,
Author_Institution :
Mater. Sci. & Eng., MIT, Cambridge, MA, USA
Abstract :
Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced CMOS thermal budget. We further investigated the ultimate thermal budget limits for the SOLES platform. We demonstrated a new SOLES structure incorporating a SiNx interlayer, which adds greater integration flexibility for future circuit applications.
Keywords :
CMOS integrated circuits; III-V semiconductors; differential amplifiers; elemental semiconductors; germanium; monolithic integrated circuits; silicon compounds; silicon-on-insulator; CMOS thermal budget; CMOS-III-V transistors; III-V-Si heterointegration; SOLES platform; Si-Ge; advanced SOI substrates; circuit applications; monolithic integration; silicon-on-lattice engineered substrates; Annealing; CMOS process; CMOS technology; Differential amplifiers; III-V semiconductor materials; Materials science and technology; Monolithic integrated circuits; Silicon; Temperature; Transistors;
