DocumentCode
2291247
Title
FD-SOI MOSFETs for the low-voltage nanoscale CMOS era
Author
Itoh, K. ; Sugii, N. ; Hisamoto, D. ; Tsuchiya, R.
Author_Institution
Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan
fYear
2009
fDate
5-8 Oct. 2009
Firstpage
1
Lastpage
4
Abstract
Limitations and challenges of FD-SOI MOSFETs are investigated in terms of intra- and inter-die Vt-variations, and capabilities of the body-bias control and multi-Vt MOSFETs. State-of-the-art planar FD-SOI MOSFETs are described, citing the SOTB (silicon on thin box) MOSFET as an example. FinFETs are also discussed; their challenges are clarified, and some solutions are proposed, such as high-density FinFETs and capacitors, and a small logic-process compatible DRAM cell. Finally, future prospects for the FD-SOI MOSFETs are presented.
Keywords
CMOS integrated circuits; MOSFET; silicon-on-insulator; DRAM cell; FD-SOI MOSFET; FinFET; body-bias control; interdie Vt-variations; intradie Vt-variations; low-voltage nanoscale CMOS era; silicon on thin box; CMOS technology; FinFETs; Laboratories; Logic circuits; Logic devices; MOSFETs; Nanoscale devices; Random access memory; Silicon; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2009 IEEE International
Conference_Location
Foster City, CA
ISSN
1078-621X
Print_ISBN
978-1-4244-4256-0
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2009.5318750
Filename
5318750
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