SOI design for a high-performance IO interface

SOI technology is well suited for high speed digital circuits. However, its history effect due to the floating body poses a major challenge to analog circuits. This paper presents the design of a high-performance IO interface (FlexIOtrade) used in Cell Broadband Enginetrade processors , currently in mass production. The design has been scaled across 90 nm, 65 nm, and 45 nm SOI CMOS processes. The parallel interface implemented in 45 nm SOI comprises 5 transmit and 5 receive bytes with each link unidirectionally running at 6.4 Gb/s achieving BER < 10^-20. The paper discusses clocking, IO, and ESD aspects of the design in SOI processes.