DocumentCode :
2291488
Title :
Physical IP design for advanced SOI technologies
Author :
Laplanche, Yves ; Pelloie, Jean-Luc ; Frey, Christophe ; Rien, Mikael
Author_Institution :
ARM-Grenoble Design Center, Grenoble, France
fYear :
2009
fDate :
5-8 Oct. 2009
Firstpage :
1
Lastpage :
4
Abstract :
The SOI technology is now mature for ASIC applications. Some foundries in the world are offering SOI technologies. ARM is enabling the ASIC design by delivering high quality physical IPs fully compatible with SOI specificities and making a bridge with traditional digital design techniques.
Keywords :
application specific integrated circuits; industrial property; integrated circuit design; silicon-on-insulator; transistors; ASIC applications; advanced SOI technologies; application specific integrated circuits; digital design techniques; partially depleted transistor; physical IP design; silicon-on-insulator; Aerospace industry; Application specific integrated circuits; Charge carrier processes; Impact ionization; Isolation technology; Random access memory; Semiconductor films; Silicon on insulator technology; Substrates; Thin film transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2009 IEEE International
Conference_Location :
Foster City, CA
ISSN :
1078-621X
Print_ISBN :
978-1-4244-4256-0
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2009.5318763
Filename :
5318763
Link To Document :
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