Wafer stacking: key technology for 3D integration

Wafer stacking technologies are today available for different 3D integration schemes. These are compatible with back end of line CMOS processes and packaging. Smart Stacking technology and copper to copper direct bonding processes were described as key technologies to realize dielectric or metallic bonding at room temperature and without applied pressure and/or additional glue layer. This results in a low stress stacked structure enabling high yield post process. Low temperature Smart Cuttrade is a third way to build 3D structures and bring opportunity to relax some stringent alignment constraints.