Analysis of sense margin and reliability of 1T-DRAM fabricated on thin-film UTBOX substrates

Author

Collaert, N. ; Aoulaiche, M. ; Rakowski, M. ; De Wachter, B. ; Bourdelle, K. ; Nguyen, B.Y. ; Boedt, F. ; Delprat, D. ; Jurczak, M.

Author_Institution

IMEC, Heverlee, Belgium

fYear

2009

fDate

5-8 Oct. 2009

Firstpage

1

Lastpage

2

Abstract

In this work, we have investigated the impact of back bias on the behavior of UTBOX IT-DRAM. The back bias impacts the behavior of undoped and doped channels differently thereby leading to different optimization schemes. It was also shown that by careful optimization of the bias conditions for both "1" but also "0", the device degradation due to hot carrier stress can be reduced significantly.

Keywords

DRAM chips; doping; hot carriers; integrated circuit reliability; optimisation; silicon-on-insulator; thin films; IT-DRAM fabrication; back bias impacts; bias conditions; device degradation; doped channel; hot carrier stress; optimization; reliability; sense margin analysis; silicon-on-insulator; thin-film UTBOX substrates; ultrathin buried oxide SOI devices; undoped channel; Charge carrier processes; Degradation; Electrons; Hot carriers; Impact ionization; Random access memory; Read-write memory; Stress; Substrates; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2009 IEEE International

Conference_Location

Foster City, CA

ISSN

1078-621X

Print_ISBN

978-1-4244-4256-0

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2009.5318781

Filename

5318781