• DocumentCode
    2291892
  • Title

    A guided tour of electronic design automation (EDA) for design of silicon on insulator (SOI) SoCs

  • Author

    Kranen, Kevin

  • Author_Institution
    Foundry & IP Alliances Program, Synopsys, Inc., Mountain View, CA, USA
  • fYear
    2009
  • fDate
    5-8 Oct. 2009
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    The design of SOI-based SoCs has traditionally been the province of a few companies that could afford very labor-intensive custom design approaches - microprocessor companies looking for performance or aerospace companies looking for rad-hard electronics. In recent years, SOI has become a more attractive option for SoC design teams that have traditionally targeted bulk silicon. With current improvements in SOI substrates, processes, devices, design IP and EDA tools, SoC design in SOI can look and feel essentially the same as design in bulk silicon. Designers can use the same familiar EDA tools and flows for bulk silicon, while achieving better performance and power results that are the hallmark of SOI.
  • Keywords
    electronic design automation; integrated circuit design; silicon; silicon-on-insulator; system-on-chip; EDA; SOI-based SoC; Si-SiO2; SoC design; bulk silicon design; electronic design automation; silicon-on-insulator; Analytical models; Electronic design automation and methodology; History; MOSFETs; Manufacturing processes; Numerical simulation; Process design; Reliability engineering; Silicon on insulator technology; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 2009 IEEE International
  • Conference_Location
    Foster City, CA
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-4244-4256-0
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2009.5318790
  • Filename
    5318790