FPGA based implementation of FDCT using Distributed Arithmetic

Author

Chowdhury, Debashis ; Samaddar, Swapan Kumar ; Sinha, Amitabha

Author_Institution

Sch. of Inf. Technol., West Bengal Univ. of Technol., Kolkata, India

fYear

2011

fDate

15-17 Sept. 2011

Firstpage

400

Lastpage

404

Abstract

The paper describes a new architecture for implementation of 8 × 8 FDCT (Fast Discrete Cosine Transform) using Distributed Arithmetic (DA). This proposed architecture combines both DA based approaches for distributed input vector and constant coefficients. The described Combined Distributed Arithmetic based DCT (CDA-DCT) architecture has been implemented on Virtex II FPGA, and shows fewer adders and saving exceeding 97% achieved.

Keywords

adders; discrete cosine transforms; distributed arithmetic; field programmable gate arrays; FPGA; adders; combined distributed arithmetic; constant coefficients; distributed input vector; fast discrete cosine transform; Adders; Clocks; Computational modeling; Computer architecture; Discrete cosine transforms; Registers; Vectors; Discrete cosine transform (DCT); Distributed arithmetic (DA); Look Up Table (LUT); Look Up Table based Accumulator (LSA);

fLanguage

English

Publisher

ieee

Conference_Titel

Computer and Communication Technology (ICCCT), 2011 2nd International Conference on

Conference_Location

Allahabad

Print_ISBN

978-1-4577-1385-9

Type

conf

DOI

10.1109/ICCCT.2011.6075190

Filename

6075190

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2291931