FDSOI for low power CMOS (invited)

As the low power technology is scaled to below 32 nm node, a number of challenges are emerging, that of scaling L (to fit at pitch) and the device leakage (GIDL and junction) . A fully depleted device can enable both L scaling and at the same time keep the GIDL much below the bulk CMOS. Significant progress has been made on FD on thin SOI. They include demonstration of devices with the right threshold (with high K) on SOI films of ~5-6 nm, and L of ~20 nm. It is argued that FDSOI can meet the requirements for a LP technology.