Novel Method for Quadrature Direct Digital Frequency Synthesizer

Author

Zhanfeng, Zhao ; Zhiquan, Zhou ; Xiaolin, Qiao

Author_Institution

Harbin Inst. of Technol.

fYear

2006

fDate

16-19 Oct. 2006

Firstpage

1

Lastpage

4

Abstract

This paper presents a novel method for quadrature direct digital frequency synthesizer with super high compression ratio which is based on the Taylor expansions. For a 32 bit-QDDFS system, 16 Gbytes´ data can be compressed to less then 2 KBytes while the SNR can get to 184 dB, so it can be realized in one CMOS chip or FPGA. The traditional DDFS architecture is changed in which accumulator is replaced by phase tipster in this system. By this excellent method, super high frequency resolution is achieved. At last, a simple configuration of this system is given

Keywords

CMOS integrated circuits; direct digital synthesis; field programmable gate arrays; 16 GBytes; 32 bits; CMOS chip; FPGA; QDDFS system; Taylor expansion; complementary metal-oxide-semiconductor; field programmable gate array; high frequency resolution; quadrature direct digital frequency synthesizer; Communication switching; Field programmable gate arrays; Frequency synthesizers; Modems; Read only memory; Signal generators; Signal to noise ratio; Spread spectrum radar; Table lookup; Taylor series; High Compression Ratio; QDDFS; Taylor expansions;

fLanguage

English

Publisher

ieee

Conference_Titel

Radar, 2006. CIE '06. International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-9582-4

Electronic_ISBN

0-7803-9583-2

Type

conf

DOI

10.1109/ICR.2006.343244

Filename

4148350