DocumentCode
2292282
Title
Improved reachability analysis of large finite state machines
Author
Cabodi, G. ; Camurati, P. ; Quer, S.
Author_Institution
Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
fYear
1996
fDate
10-14 Nov. 1996
Firstpage
354
Lastpage
360
Abstract
BDD-based symbolic traversals are the state-of-the-art technique for reachability analysis of finite state machines. They are currently limited to medium-small circuits for two reasons: peak BDD size during image computation and BDD explosion for representing state sets. Starting from these limits, this paper presents can optimized traversal technique particularly oriented to the exact exploration of the state space of large machines. This is possible thanks to: temporary simplification of a finite state machine by removing some of its state elements; and a "divide-and-conquer" approach based on state set decomposition. An effective use of secondary memory allows us to store relevant portions of BDDs and to regularize access to memory, resulting in less page faults. Experimental results show that this approach is particularly effective on the larger ISCAS\´89 and ISCAS\´89-addendum\´93 circuits.
Keywords
circuit diagrams; circuit optimisation; circuit testing; divide and conquer methods; finite state machines; logic CAD; logic testing; binary decision diagrams; divide-and-conquer; image computation; large finite state machines; logic design; optimized traversal technique; page faults; reachability analysis; secondary memory; state set decomposition; symbolic traversals; Automata; Binary decision diagrams; Boolean functions; Circuit faults; Data structures; Explosions; Image converters; Latches; Reachability analysis; State-space methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
Print_ISBN
0-8186-7597-7
Type
conf
DOI
10.1109/ICCAD.1996.569819
Filename
569819
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