A 3.3V to 3.19V low-dropout regulator with frequency compensation strategy without trimming

Author

Zhang, Yiwei ; Liu, Liyuan ; Li, DongMei

Author_Institution

Instn. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2011

fDate

6-7 Oct. 2011

Firstpage

17

Lastpage

20

Abstract

This paper introduces a 3.3V to 3.19V low-dropout regulator (LDO) with frequency compensation strategy implemented in 0.18μm 1P6M COMS process. The LDO circuit has the frequency compensation strategy to keep stable. There is a bandgap designed in the LDO to generate the reference voltage and the bias current for the LDO. The maximum output current of the LDO is 70mA when the output voltage could reach 3.18V And the output voltage of the LDO could still reach 3.19V, where the supply voltage is 3.20V and the output current is 0.8mA. The quiescent current is 0.04mA when there is no output current and the VDD voltage is 3.3V Because the LDO of this paper could change the power supply from 3.3V to 3.19V, the dropout voltage is only 0.11V and the power efficiency could be increased significantly. The active core area of the LDO is 0.46mm×0.7mm and the whole area is 0.86mm×1.1mm.

Keywords

CMOS integrated circuits; compensation; frequency control; power supplies to apparatus; voltage regulators; 1P6M COMS process; LDO circuit; VDD voltage; bandgap design; frequency compensation strategy; low-dropout regulator; maximum output current; power efficiency; power supply; quiescent current; size 0.18 mum; voltage 3.3 V to 3.19 V; CMOS integrated circuits; Capacitors; Circuit stability; Photonic band gap; Power supplies; Regulators; Stability criteria;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2011 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Macau

ISSN

2159-2144

Print_ISBN

978-1-4577-1608-9

Type

conf

DOI

10.1109/PrimeAsia.2011.6075218

Filename

6075218