ASIC implementation of a direct-sequence spread-spectrum RAKE-receiver

Presents the design of two application-specific integrated circuits (ASIC) for spread-spectrum wireless local area networks (WLAN) providing data rates up to 2 Mb/s. The first device is a chip matched filter, which performs square root raised cosine transmit/receive filtering, while the second implements complex correlations and coherent BPSK/QPSK demodulation. The coefficients of the chip matched filter are represented as canonic signed digits (CSD) in order to reduce chip size and allow sampling rates up to 100 MHz. The second ASIC contains six independent complex correlators for channel sounding and despreading. Four RAKE arms are used for data detection by coherently combining the signals from the strongest propagation paths. Special attention has been given to the tradeoff between chip area and system performance (bit error probability) through careful choice of word lengths for each processing stage