An integrated framework for optimizing transformations

This paper proposes a framework aimed at the optimization of speed, area, or power consumption of custom ASIC DSP designs through algorithmic transformations. This framework systematically selects and orders transformations for optimization. The methodology behind the framework combines bottleneck analysis (why the transformations should be applied), transformation ordering (the order in which the transformations are applied), algorithm partitioning (which parts of an algorithm should be transformed), transformation analysis/selection (which transformations to apply), and transformation execution (how to apply the selected transformations). Assisted by this framework, designers can easily and quickly exploit a variety of optimizing transformations to explore the algorithmic design space to reach better designs