Title :
An algorithm for synthesis of system-level interface circuits
Author :
Chung, K.-S. ; Gupta, R.K. ; Liu, C.L.
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with fixed interfaces. The algorithm accepts the timing characteristics of two system components as input, and generates a combinational interface (glue logic) circuit. The algorithm consists of two parts. In the first part, we determine the direct pin-to-pin connections in the interface circuit employing a 0/1 ILP formulation to minimize wiring area and dynamic power consumption. In the second part, we determine logic subcircuits in the interface circuit, utilizing the timing diagrams of the system components. The proposed algorithm has been implemented in a software package SYNTERFACE. Experimental results are presented to demonstrate the effectiveness of the algorithm.
Keywords :
application specific integrated circuits; circuit optimisation; logic CAD; power consumption; real-time systems; 0/1 ILP formulation; combinational interface; direct pin-to-pin connections; dynamic power consumption; embedded system; glue logic circuit; logic subcircuits; memory ASIC; microprocessors; network subsystems; optimization; software package SYNTERFACE; system-level interface circuits synthesis; timing characteristics; timing diagrams; wiring area; Application specific integrated circuits; Character generation; Circuit synthesis; Combinational circuits; Embedded system; Energy consumption; Microprocessors; Network synthesis; Timing; Wiring;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569835
