DocumentCode :
2295106
Title :
Minimum spanning tree on the HMESH architecture
Author :
Boppana, R.V. ; Raghavendra, C.S.
Author_Institution :
Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1988
fDate :
10-12 Oct 1988
Firstpage :
121
Lastpage :
124
Abstract :
A fast algorithm to compute the minimum spanning tree of a given undirected graph on a hierarchical mesh-connected computer (HMESH) is presented. The time complexity of the algorithm is O(log2 n), where n is the number of nodes in the graph. HMESH is a broadcast bus VLSI architecture which consists of n× n processing elements (PEs) in a mesh-connected structure and a hierarchy of broadcast buses in each row and column of the mesh structure such that each broadcast bus is connected to exactly k PE´s, where k is a small constant. It is shown that with simple modifications to the algorithm, the MST of an n node graph can be found on a HMESH of size p×p in O[n/p]2 log n log p) time. It is also shown how to compute connected components and transitive closure of a given undirected graph in O(log2 n) with a few modifications to the algorithm presented for computing the minimum spanning tree
Keywords :
VLSI; computational complexity; parallel algorithms; trees (mathematics); HMESH architecture; broadcast bus VLSI architecture; connected components; fast algorithm; mesh-connected structure; minimum spanning tree; processing elements; time complexity; transitive closure; undirected graph; Broadcasting; Cities and towns; Computer architecture; Concurrent computing; Costs; Joining processes; Parallel algorithms; Phase change random access memory; Tree graphs; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Frontiers of Massively Parallel Computation, 1988. Proceedings., 2nd Symposium on the Frontiers of
Conference_Location :
Fairfax, VA
Print_ISBN :
0-8186-5892-4
Type :
conf
DOI :
10.1109/FMPC.1988.47422
Filename :
47422
Link To Document :
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