DocumentCode
2295128
Title
Instruction cache prefetching with extended BTB
Author
Chi, Shyh-An ; Shiu, R-Ming ; Chiu, Jih-ching ; Chang, Si-En ; Chung, Chung-Ping
Author_Institution
Dept. of Comput. Sci. & Inf. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
1997
fDate
10-13 Dec 1997
Firstpage
360
Lastpage
365
Abstract
Instruction cache prefetching is a technique to reduce the penalty caused by instruction cache misses. The prefetching methods generally determine the target line to be prefetched based on the current fetched line address. However, as the cache line becomes wider, there may be multiple branches in a cache line which hurdles the decision made by these methods. This paper develops a new instruction cache prefetching method in which the prefetch is directed by the prediction on branches. We call it the branch instruction based (BIB) prefetching. In BIB prefetching, the prefetch information is recorded in an extended BTB. Simulation results show that, the BIB prefetching outperforms the traditional sequential prefetching by 7% and other prediction table based prefetching methods by 17% on average. As the BTB designs become more sophisticated and achieve higher hit and accuracy ratio, the BIB prefetching can achieve higher performance
Keywords
cache storage; digital simulation; instruction sets; performance evaluation; branch instruction based prefetching; fetched line address; instruction cache misses; instruction cache prefetching; instruction cache prefetching method; simulation results; Clocks; Computer aided instruction; Computer science; Contracts; Degradation; Microprocessors; Predictive models; Prefetching; System performance; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Systems, 1997. Proceedings., 1997 International Conference on
Conference_Location
Seoul
Print_ISBN
0-8186-8227-2
Type
conf
DOI
10.1109/ICPADS.1997.652574
Filename
652574
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