Title :
Design of adaptive mesh routing chip
Author_Institution :
Comput. Res. Group, Electron. & Telecommun. Res. Inst., Taejon, South Korea
Abstract :
Design of an adaptive router chip with minimum possible delay is described. The designed router is for message passing between computers which are connected in 2D mesh topology. The implemented algorithm is the negative-first adaptive wormhole routing algorithm which is deadlock free, livelock free, minimal, and maximally adaptive. The functional blocks of the router and asynchronous interfaces between routers were verified with VHDL modeling and simulation. Future enhancements for dynamic fault handling features are discussed
Keywords :
computer networks; fault diagnosis; hardware description languages; logic testing; message passing; multiprocessing systems; network topology; sequential circuits; telecommunication computing; telecommunication network routing; 2D mesh topology; VHDL modeling; VHDL simulation; adaptive mesh routing chip; asynchronous interfaces; asynchronous sequential logic circuits; delay; dynamic fault handling; livelock free algorithm; maximally adaptive algorithm; message passing; multicomputers; negative-first adaptive wormhole routing algorithm; Adaptive algorithm; Communication networks; Communication switching; Delay; Message passing; Network topology; Routing; System recovery; Tail; Telecommunication computing;
Conference_Titel :
Singapore ICCS '94. Conference Proceedings.
Print_ISBN :
0-7803-2046-8
DOI :
10.1109/ICCS.1994.474248
