A high-speed interconnect network using ternary logic

This paper describes the design and implementation of a high-speed interconnect network (ICN) for a multiprocessor system using ternary logic. By using ternary logic and a fast point-to-point communication technique called STARI (Self-Timed At Receiver´s Input), the communication between the processors is free of clock skew and insensitive to any delay differences in buffers and wires. In addition, the number of signal wires and pins are reduced by 50 percent in comparison with a similar binary implementation. The ICN architecture is based on a crossbar topology and the high-speed part consists of two LSI GaAs chips, Interface and Crossbar, which were implemented in a 0.8 μm MESFET process. In a 4×4 ICN, communication at 300 Mbit/s per wire was demonstrated, which is twice as fast as pure synchronous and four times faster than pure asynchronous communication in the specific test set-up