Title :
Random pattern fault simulation in multi-valued circuits
Author :
Drechsler, Rolf ; Krieger, Rolf ; Becker, Bernd
Author_Institution :
Dept. of Comput. Sci., Frankfurt Univ., Germany
Abstract :
We present a fault simulator for Multi-Valued Logic Networks (MVLN). With this tool we investigate their Random Pattern Testability (RPT). We show for a restricted class of multi-valued circuits that the RPT is better than for two-valued circuits. We point out the relation between redundancies in two- and multi-valued logic networks. Moreover we show that the role of fault simulation for MVLNs is more important than in the binary case. A set of experimental results for large circuits emphasizes the efficiency of our approach
Keywords :
circuit analysis computing; fault diagnosis; integrated circuit testing; logic testing; multivalued logic circuits; fault simulator; multi-valued circuits; multi-valued logic networks; random pattern fault simulation; random pattern testability; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Electrical fault detection; Fault detection; Logic testing; Multivalued logic; Redundancy;
Conference_Titel :
Multiple-Valued Logic, 1995. Proceedings., 25th International Symposium on
Conference_Location :
Bloomington, IN
Print_ISBN :
0-8186-7118-1
DOI :
10.1109/ISMVL.1995.513516
