A compact low-power decimation filter for sigma delta modulators

Sigma delta modulators can provide the lowest power and area solution for high resolution A/D converters. Unfortunately the required decimation filter for the modulator tends to consume much more power and area than the modulator. This paper solves both problem by introducing a new FIR-Sinc architecture and taking advantage of the low number of bits at the input. Careful choice of pipelining and logic style and the use of multiple-V_DD logic lead to a low power implementation without compromising on performance and area. The power consumed is 93% less and area used is 14% less than the best reported designs. The 64-tap programmable decimation filter with 10-bit coefficients consumes 1.5 mW of power and 0.71 mm² of area running on a 40 MHz 1.5 bit input with a 1.25 MHz 15 bit output on a 1.65 V supply