A study of stratified sampling in variance reduction techniques for parametric yield estimation

Author

Keramat, Mansour ; Kielbasa, Richard

Author_Institution

Service des Mesures, Ecole Superieure d´´Electr., Gif-sur-Yvette, France

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1652

Abstract

In the literature, several variance reduction techniques in Monte Carlo circuit yield estimation have been described, e.g., stratified sampling. In this contribution the theoretical aspects of partitioning scheme of the tolerance region in stratified sampling is presented. To the best of our knowledge, this problem was not previously studied in parametric yield estimator. The proposed stratified sampling Monte Carlo yield estimator has always a smaller or equal variance with respect to Primitive Monte Carlo (PMC) yield estimator

Keywords

Monte Carlo methods; circuit CAD; circuit optimisation; integrated circuit design; integrated circuit yield; IC design; Monte Carlo circuit yield estimation; parametric yield estimation; partitioning scheme; stratified sampling; tolerance region; variance reduction techniques; Circuit simulation; Costs; Electronic circuits; Hypercubes; Ink; Integrated circuit modeling; Monte Carlo methods; Probability distribution; Sampling methods; Yield estimation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621450

Filename

621450