Approximate analysis of asymmetric packet switch modules under bursty and nonuniform traffic environment

This paper analyses the performance of output channel grouped asymmetric packet switch modules in ATM networks, under geometrically bursty input traffic with input/output traffic imbalance. The switch module considered has n inputs and m outputs. A packet destined for a particular output address (out of g) needs to access only one of the r available physical output ports; m=gr. The motivation for the study of these switch modules is that they are the key building blocks in many huge multistage switch architectures. A combination of exact derivation and numerical analysis yields the saturation throughput of input buffered switch modules for a wide range of traffic nonuniformity factors and burstiness. Results show a degradation in the maximum throughput as the average burst length increases and this is found to be true for any traffic nonuniformity factor. Throughput degradation due to head-of-line blocking is found to be the largest when switch modules are symmetric (gr=n). Thus, asymmetric switches tend to diminish the throughput advantage of output-buffered switch modules over input-buffered switch modules and this is true for any combination of input/output traffic imbalance and burst length. Our results also indicate that increasing the number of output ports per output address can significantly improve the switch performance, especially when traffic is highly nonuniform and bursty