System-level performance estimation strategy for sw and hw

Author

Alla, A. ; Brandolese, C. ; Fornaciari, W. ; Salice, F. ; Sciuto, D.

Author_Institution

Central Res. Labs., ITALTEL, Italy

fYear

1998

fDate

5-7 Oct 1998

Firstpage

48

Lastpage

53

Abstract

The design of an embedded system is a process where the tuning of the architecture should take into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw components. The goal of this paper is to present the new model developed during the SEED Esprit project, to estimate the software and hardware characteristics for cosimulation and profiling within the TOSCA codesign framework. The impact on the design space exploration of such an high-level cosimulation strategy has been tested by considering as a benchmark the reengineering of an industrial device

Keywords

embedded systems; hardware-software codesign; systems re-engineering; timing; SEED Esprit project; TOSCA codesign framework; cosimulation; design space exploration; embedded system; high-level cosimulation strategy; system-level performance estimation strategy; timing performance; tuning; Aerospace industry; Analytical models; Design automation; Electrical capacitance tomography; Embedded system; Process design; Space exploration; Space technology; Testing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-9099-2

Type

conf

DOI

10.1109/ICCD.1998.727022

Filename

727022