DocumentCode
2296795
Title
DARPA sensor national testbed: hardware and software architecture
Author
Guarino, D.R. ; Kruger, R.P. ; Sayre, S. ; Sos, T. ; Turner, C.J. ; Winter, C.L.
Author_Institution
Sci. Applications Int. Corp., Tucson, AZ, USA
fYear
1988
fDate
10-12 Oct 1988
Firstpage
295
Lastpage
301
Abstract
A heterogeneous network of parallel computers developed for complex distributed-processing applications is described. Network computers include a Connection Machine, a Butterfly multiprocessor, a WARP systolic array, and a Symbolics and several SUN workstations. An Ethernet and a high-bandwidth APTEC bus support data transfers. Distributed applications are built from individual processes executing on computers in the network. A powerful asynchronous communication facility is built upon the multiple computer operating systems to provide uniform message passing, global memory variables, and remote process execution services to processes. An executive controller and the LISP+ functional language provide a method of integrating distributed processes into an application with transparent control of network resources and communications. Additional applications can be rapidly built from existing processing to support experiments in distributed and parallel applications
Keywords
computer networks; distributed processing; network operating systems; parallel processing; Butterfly multiprocessor; Connection Machine; DARPA sensor national testbed; Ethernet; LISP+ functional language; SUN workstations; Symbolics; WARP systolic array; asynchronous communication facility; data transfers; distributed processes; distributed-processing applications; global memory variables; heterogeneous network of parallel computers; high-bandwidth APTEC bus; multiple computer operating systems; network resources; parallel applications; remote process execution services; transparent control; uniform message passing; Application software; Communication system control; Computer networks; Concurrent computing; Distributed computing; Hardware; Software architecture; Software testing; Sun; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Frontiers of Massively Parallel Computation, 1988. Proceedings., 2nd Symposium on the Frontiers of
Conference_Location
Fairfax, VA
Print_ISBN
0-8186-5892-4
Type
conf
DOI
10.1109/FMPC.1988.47433
Filename
47433
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