A low-power logic optimization methodology based on a fast power-driven mapping

This paper describes a novel technique of integrating a fast power-driven mapper with structural optimizations that target low power consumption. The power-driven mapping technique is based on the decomposed factored form representation of Boolean expressions. The power cost function based on this mapped netlist is more accurate than the previous cost functions. It is used to guide the structural transformations in our low-power driven logic synthesis tool. Circuits synthesized by the area optimization tool, SIS, consume on an average 54.5% more power and require 21.9% more area than those obtained by our tool. Finally, results obtained from the power optimization tool, POSE, are on the average 10.4% and 5.6% inferior in power consumption and area respectively to those obtained by our tool