WSD: Self-interference and co-habitation considerations in complex SoC and SiP integrated solutions

With the integration of RF, mixed signal and digital building blocks on a single die, combined with the trend of increased frequencies (both in the RF and in the digital circuitry), it is essential to consider various on-chip coupling effects in the early design phases of the RF SoC or SiP. Additionally, provisions should be made for mitigating the impact of peripheral interactions (e.g., package, antenna), as well as the potential for self- interference, such that these are either eliminated or can be resolved on the fabricated product without hardware redesign. The focus of this interactive workshop will be on resolving self-interference problems: on-chip coupling effects, chip-package co-design, substrate issues, coupling-aware RFIC floor planning, digitally assisted solutions for interference problems, design practices, modeling and CAD/EDA capabilities to address coupling effects. Recognized companies and partnerships active in the semiconductor industry will present actual issues encountered in their designs and the solutions/design-practices used to address them. Interactive discussions will be facilitated to exchange valuable ideas for the benefit of participants and the industry at large.