Title :
Adaptive synchronization
Author :
Ginosar, Ran ; Kol, Rakefet
Author_Institution :
VLSI Syst. Res. Center, Technion-Israel Inst. of Technol., Haifa, Israel
Abstract :
Delay variations are typically accounted for by increasing cycle time margins. Adaptive synchronization eliminates this on inter-modular interfaces in very large, high performance chips. The chip is divided into multiple smaller synchronous modules. Multi-synchronous hierarchical clocking provides the same frequency to all modules, but does not maintain any particular phase. Adaptive synchronizers adapt to the time-varying inter-modular clock and data phases, and out-perform conventional synchronizers
Keywords :
clocks; logic design; synchronisation; timing jitter; adaptive synchronization; cycle time margins; data phases; delay variations; high performance chips; inter-modular interfaces; multi-synchronous hierarchical clocking; time-varying inter-modular clock; Clocks; Delay effects; Frequency synchronization;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-8186-9099-2
DOI :
10.1109/ICCD.1998.727042
