High-performance digit-serial complex-number multiplier-accumulator

Author

Chang, Yun-Nan ; Parhi, Keshab K.

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

fYear

1998

fDate

5-7 Oct 1998

Firstpage

211

Lastpage

213

Abstract

This paper presents a fast highly regular digit-serial complex-number multiplier-accumulator (CMAC) architecture which is well suited for VLSI implementations. This paper makes two contributions. First, several complex-number representation schemes are discussed. It is shown that the real-imaginary alternate (RIA) scheme is the best among all representation schemes and the prior designs of CMACs based on the radix-(2j) redundant complex number system (RCNS) are not efficient with respect to hardware complexity and processing speed. Second, digit-serial CMAC architectures which can be pipelined at fine-grain level to increase the throughput rate are designed based on carry-save configuration

Keywords

VLSI; adders; computational complexity; digital arithmetic; VLSI implementations; carry-save configuration; hardware complexity; high-performance digit-serial complex-number multiplier-accumulator; processing speed; real-imaginary alternate scheme; redundant complex number system; Adders; Arithmetic; Computer architecture; Convolution; Design methodology; Digital communication; Hardware; Signal processing algorithms; Throughput; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-9099-2

Type

conf

DOI

10.1109/ICCD.1998.727050

Filename

727050