DocumentCode
2297333
Title
A minimized hardware architecture of fast Phong shader using Taylor series approximation in 3D graphics
Author
Shin, Hyun-Chul ; Lee, Jin-Aeon ; Kim, Lee-Sup
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fYear
1998
fDate
5-7 Oct 1998
Firstpage
286
Lastpage
291
Abstract
One of the most successful algorithms that bring realism to the world of 3D-image generation is Phong shading. But, Gouraud shading has been used instead of Phong shading because of per pixel computation and hardware costs. However, with continuous improvement of VLSI technologies and request for higher realism, real-time Phong shading will be the next technology-push in 3D graphics. Taylor series approximation is an algorithm of fast Phong shading algorithms that is appropriate for hardware implementation. But, the hardware implementation of this algorithm requires a large ROM table that induces an overhead in terms of hardware size. We reduced this overhead by minimizing the ROM table size while keeping visual quality through visual comparison. We minimized a large ROM table size of a uniform quantization method to 1/64 using an adaptive-compressed non-uniform quantization method. By minimizing the ROM table size, we could minimize the total hardware size to 1/56
Keywords
computer graphic equipment; image processing; logic design; 3D graphics; 3D-image generation; ROM table; Taylor series approximation; fast Phong shader; hardware architecture; hardware implementation; Approximation algorithms; Computational efficiency; Computer architecture; Continuous improvement; Graphics; Hardware; Quantization; Read only memory; Taylor series; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1998. ICCD '98. Proceedings. International Conference on
Conference_Location
Austin, TX
ISSN
1063-6404
Print_ISBN
0-8186-9099-2
Type
conf
DOI
10.1109/ICCD.1998.727063
Filename
727063
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